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<p>Proposes a new algorithm of estimation and compensation of the error effect for rounding in the case of implementation of division and square root using the Newton-Raphson method. The authors analyze the error of the hardware system to confirm the condition of the implementation with respect to this algorithm. Next, they describe in detail how to compensate the error by using this algorithm. Finally, they show that the hardware components for this algorithm, the direct rounding mechanism in the recode circuit and the sticky digit generating circuit, can be realized simply by improving the redundant binary representation multiplier. The number of increasing cycles for this new algorithm is only one, and the rounding result using this algorithm satisfies IEEE Standard 754 rounding perfectly.</p>
digital arithmetic; error analysis; rounding scheme; Newton-Raphson method; redundant binary representation; error effect; recode circuit; sticky digit generating circuit; redundant binary representation multiplier.
H. Yamashita, A. Miyoshi, S. Kuninobu, H. Edamatsu, M. Urano, H. Kabuo, T. Taniguchi, "Accurate Rounding Scheme for the Newton-Raphson Method Using Redundant Binary Representation", IEEE Transactions on Computers, vol. 43, no. , pp. 43-51, January 1994, doi:10.1109/12.250608
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