Design of a Fault-Tolerant Three-Dimensional Dynamic Random-Access Memory with On-Chip Error-Correcting Circuit
Issue No. 12 - December (1993 vol. 42)
DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/12.260635
<p>Most current-generation multimegabit dynamic random-access memory (DRAM) chips use three-dimensional storage capacitors where the charge is stored on a vertically integrated trench-type structure and are highly vulnerable to alpha particles, which frequently create plasma shorts between two adjoining trench capacitors on the same word line, resulting in uncorrectable double-bit soft errors. The author presents a systematic study of soft-error related problems and discusses methodologies for correcting single-bit and double-bit memory-cell upsets by using on-chip error-correcting-code (ECC) circuits. By modifying the product code, an effective coding scheme has been designed that can be integrated within a DRAM chip to correct double-bit errors. It is demonstrated that the reliability of a memory chip can be improved by several million times by integrating the proposed circuit. The area and timing overhead are calculated and compared with those of memory chips without any ECC and chips with single-error-correcting (SEC) codes. The ability of the circuit to correct soft errors in the presence of multiple-bit errors is analyzed.</p>
DRAM chips; error correction codes; fault tolerant computing; fault-tolerant three-dimensional dynamic random-access memory; on-chip error-correcting circuit; storage capacitors; plasma shorts; double-bit soft errors; memory-cell upsets; error-correcting-code.
P. Mazumder, "Design of a Fault-Tolerant Three-Dimensional Dynamic Random-Access Memory with On-Chip Error-Correcting Circuit", IEEE Transactions on Computers, vol. 42, no. , pp. 1453-1468, December 1993, doi:10.1109/12.260635