Issue No. 11 - November (1993 vol. 42)
DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/12.247840
<p>Wafer packing is a process of combining multiple chip designs on the same wafer such that the fabrication cost can be shared by several designs and hence reduced. This technique is widely used for designs that require a small number of dies or chips. It is essential to have computer algorithms to decide how to allocate designs to wafers in order to reduce the total fabrication cost. Based on different wafer fabrication techniques, two versions of the wafer packing problem are formulated. The authors study different variations for each version. They present algorithms to find optimal solutions for these variations which are polynomial-time solvable. They also present heuristic algorithms for those proven to be NP-hard. The effectiveness of the proposed algorithms is demonstrated by experimental results.</p>
wafer-packing problems; multiple chip designs; fabrication cost; polynomial-time solvable; heuristic algorithms; NP-hard; VLSI design; multichip modules; VLSI.
D. Du, I. Lin and K. Chang, "On Wafer-Packing Problems," in IEEE Transactions on Computers, vol. 42, no. , pp. 1382-1388, 1993.