Issue No. 11 - November (1993 vol. 42)

ISSN: 0018-9340

pp: 1361-1371

DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/12.247839

ABSTRACT

<p>This paper presents an efficient sequential circuit automatic test generation algorithm. The algorithm is based on PODEM and uses a nine-valued logic model. Among the novel features of the algorithm are use of Initial Timeframe Algorithm and correct implementation of a solution to the Previous State Information Problem. The Initial Timeframe Algorithm, one of the most important aspects of the test generator, determines the number of timeframes required to excite the fault for which a test is to be derived and the number of timeframes required to observe the excited fault. Correct determination of the number of timeframes in which the fault should be excited (activated) and observed saves the test generator from performing unnecessary search in the input space. Test generation is unidirectional, i.e., it is done strictly in forward time, and flip-flops in the initial timeframe are never assigned a state that needs to be justified later. The algorithm saves both the good and the faulty machine states after finding a test to aid in subsequent test generation. The Previous State Information Problem, which has often been ignored by existing test generators, is presented and discussed in the paper. Experimental results are presented to demonstrate the effectiveness of the algorithm.</p>

INDEX TERMS

sequential circuit test generation; automatic test generation algorithm; PODEM; nine-valued logic model; Initial Timeframe Algorithm; Previous State Information Problem; faulty machine states; automatic testing; logic testing; sequential circuits.

CITATION

K.K. Saluja, S.Y. Lee, T.P. Kelsey, "An Efficient Algorithm for Sequential Circuit Test Generation",

*IEEE Transactions on Computers*, vol. 42, no. , pp. 1361-1371, November 1993, doi:10.1109/12.247839