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<p>A lower bound AT/sup 2/= Omega (n/sup 2/) for the conversion from positional to residue representation is derived according to VLSI complexity theory, and existing solutions for the same problem are briefly reviewed in the light of such a bound. A VLSI system is proposed, one that operates according to a pipeline scheme and works asymptotically emulating an optimal structure, independently of residue number system parameters. This solution has been applied to a design of specific size (64-b input stream), and it has been found that a single CMOS custom chip can implement the design with a throughput of one residue representation every 30-40 ns.</p>
weighted representation; lower bound; VLSI complexity; number conversion; residue representation; pipeline scheme; optimal structure; single CMOS custom chip; CMOS integrated circuits; computational complexity; digital arithmetic; VLSI.
G. Alia, E. Martinelli, "On the Lower Bound to the VLSI Complexity of Number Conversion from Weighted to Residue Representation", IEEE Transactions on Computers, vol. 42, no. , pp. 962-967, August 1993, doi:10.1109/12.238486
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