Issue No. 03 - March (1993 vol. 42)
DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/12.210169
<p>Test-equivalent faults are commonly used in test generation and fault simulation to reduce the number of explicitly addressed faults. At the gate level, practical equivalence rules are confined to faults on the input and output terminals of Boolean gates and those related to fanout-free wires. It is shown that under some conditions equivalence may also be stated between faults on a fanout stem and its branches. A modification of the standard fault folding algorithm is proposed, which leads to reducing the number of target faults and occasionally identifying logic redundancies. Application to real designs shows that the added computational complexity is negligible, while for some classes of CMOS circuits hard-to-simulate faults are eliminated and hence their fault simulation time is drastically reduced.</p>
fanout-point faults; test generation; fault simulation; explicitly addressed faults; gate level; equivalence rules; Boolean gates; fanout-free wires; logic redundancies; computational complexity; CMOS circuits; fault simulation time; CMOS integrated circuits; computational complexity; integrated logic circuits; logic design; logic testing.
A. Lioy, "On the Equivalence of Fanout-Point Faults", IEEE Transactions on Computers, vol. 42, no. , pp. 268-271, March 1993, doi:10.1109/12.210169