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<p>An accelerated fault simulation approach for path delay faults is presented. The distinct features of the proposed fault simulation method consist in the application of parallel processing of patterns at all stages of the calculation procedure, its versatility to account for both robust and nonrobust decision of path delay faults, and its capability of efficiently maintaining large numbers of path faults to be simulated.</p>
path delay fault simulation; parallel processing; patterns; circuit analysis computing; fault location; integrated circuit testing; many-valued logics; parallel processing.

F. Fink, M. Schulz and K. Fuchs, "Robust and Nonrobust Path Delay Fault Simulation by Parallel Processing of Patterns," in IEEE Transactions on Computers, vol. 41, no. , pp. 1527-1536, 1992.
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