Issue No. 12 - December (1992 vol. 41)
DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/12.214660
<p>FOCUS, a simulation environment for conducting fault-sensitivity analysis of chip-level designs, is described. The environment can be used to evaluate alternative design tactics at an early design stage. A range of user specified faults is automatically injected at runtime, and their propagation to the chip I/O pins is measured through the gate and higher levels. A number of techniques for fault-sensitivity analysis are proposed and implemented in the FOCUS environment. These include transient impact assessment on latch, pin and functional errors, external pin error distribution due to in-chip transients, charge-level sensitivity analysis, and error propagation models to depict the dynamic behavior of latch errors. A case study of the impact of transient faults on microprocessor-based jet-engine controller is used to identify the critical fault propagation paths, the module most sensitive to fault propagation, and the module with the highest potential for causing external errors.</p>
fault sensitivity analysis; FOCUS; simulation environment; chip-level designs; alternative design tactics; user specified faults; chip I/O pins; transient impact assessment; functional errors; external pin error distribution; in-chip transients; charge-level sensitivity analysis; error propagation models; dynamic behavior; latch errors; transient faults; microprocessor-based jet-engine controller; critical fault propagation paths; circuit analysis computing; circuit CAD; design for testability; fault location; microcontrollers; VLSI.
G.S. Choi, R.K. Iyer, "FOCUS: An Experimental Environment for Fault Sensitivity Analysis", IEEE Transactions on Computers, vol. 41, no. , pp. 1515-1526, December 1992, doi:10.1109/12.214660