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<p>The reliability of systems that employ fault tolerance at two different hierarchical levels is considered. It is assumed that the system consists of a two-dimensional array of components. Each component is reliable as long as it has been afflicted by no more than t faults; when t+1 faults occur in a particular component, the component ceases to be reliable. Furthermore, the system remains operative as long as no more than one component in any row is unreliable. Generalizing the techniques used to analyze the well-known 'birthday surprise' problem of applied probability makes it possible to derive an approximation to the average number of faults needed until the system fails. Applications include random access memory systems with chip-level and board-level coding as well as fault-tolerant systolic arrays.</p>
chip level coding; reliability; fault tolerance; hierarchical levels; two-dimensional array; random access memory systems; board-level coding; fault-tolerant systolic arrays; encoding; fault tolerant computing; random-access storage; systolic arrays.

G. Yang and T. Fuja, "The Reliability of Systems with Two Levels of Fault Tolerance: The Return of the 'Birthday Surprise'," in IEEE Transactions on Computers, vol. 41, no. , pp. 1490-1496, 1992.
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