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<p>The worst-case carry propagation delays in carry-skip adders and block carry-lookahead adders depend on how the full adders are grouped structurally together into blocks as well as the number of levels. The authors report on a multidimensional dynamic programming paradigm for configuring these two adders to attain minimum latency. Previous methods are applicable only to very limited delay models that do not guarantee a minimum latency configuration. Under the delay model, critical path delay is calculated not only taking into account the intrinsic gate delays, but also the fanin and fanout contributions.</p>
delay optimisation; carry-skip adders; block carry-lookahead adders; multidimensional dynamic programming; worst-case carry propagation delays; minimum latency; critical path delay; gate delays; fanin; fanout; adders; carry logic; digital arithmetic; dynamic programming.

P. Chan, V. Oklobdzija, C. Thomborson and M. Schlag, "Delay Optimization of Carry-Skip Adders and Block Carry-Lookahead Adders Using Multidimensional Dynamic Programming," in IEEE Transactions on Computers, vol. 41, no. , pp. 920-930, 1992.
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