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<p>Methods for modeling and implementing various practical aspects of fault-tolerant multiprocessor systems largely neglected in prior research are examined. The node-covering design approach is generalized to accommodate systems whose structure and failure mechanisms are represented by arbitrary graphs. Several new types of covering graphs are defined, which lead to various useful design tradeoffs. A new technique for incremental design is presented, using a class of switch implementations that reduce a system's interconnection costs. The reduction of other cost factors is also addressed, and methods are presented for VLSI layout area minimization, fast and distributed reconfiguration, efficient transfer of state information for software recovery, and the efficient use of local spares.</p>
fault-tolerant multiprocessors; node-covering design; covering graphs; incremental design; VLSI layout area minimization; distributed reconfiguration; state information; software recovery; local spares; circuit layout CAD; computational complexity; fault tolerant computing; graph theory; multiprocessing systems; parallel algorithms; VLSI.

J. Hayes and S. Dutt, "Some Practical Issues in the Design of Fault-Tolerant Multiprocessors," in IEEE Transactions on Computers, vol. 41, no. , pp. 588-598, 1992.
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