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<p>Reconfigurable logic and memory structures are an important means of increasing manufacturing yield as both circuit density and chip size continue to increase. Yield enhancement through reconfiguration, however, necessarily relies on accurate diagnosis of fault locations. Although a substantial body of literature exists concerning testing of logic arrays, little is known regarding diagnosis of the specific locations of multiple faults in such arrays. In the paper a fault diagnosis algorithm is presented for large programmable logic arrays (PLAs).</p>
reconfigurable logic; reconfigurable PLAs; fault location; spare allocation; yield enhancement; memory structures; manufacturing yield; circuit density; chip size; multiple faults; fault diagnosis algorithm; programmable logic arrays; circuit reliability; computational complexity; fault tolerant computing; logic arrays.

S. Kuo and W. Fuchs, "Fault Diagnosis and Spare Allocation for Yield Enhancement in Large Reconfigurable PLAs," in IEEE Transactions on Computers, vol. 41, no. , pp. 221-226, 1992.
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