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<p>The authors propose a general synthesis method for efficiently implementing any family of Boolean functions over a set of variables, as a self-timed logic module. Interval temporal logic is used to express the constraints that are formulated for the self-timed logic module. A method is provided for proving the correct behavior of the designed circuit, by showing that it obeys all the functional constraints. The resulting circuit is compared with alternative proposed self-timed methodologies. This approach is shown to require less gates than other methods. The proposed method is appropriate for automatic synthesis of self-timed systems. A formal proof of correctness is provided.</p>
Boolean functions; self-timed circuits; logic module; temporal logic; functional constraints; automatic synthesis; formal proof; correctness; Boolean functions; logic circuits; logic design; temporal logic.

M. Yoeli, R. Ginosar and I. David, "An Efficient Implementation of Boolean Functions as Self-Timed Circuits," in IEEE Transactions on Computers, vol. 41, no. , pp. 2-11, 1992.
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