Issue No. 12 - December (1991 vol. 40)
DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/12.106224
<p>Implementations of neural networks on programmable massively parallel computers are addressed. The methods are based on a graph theoretic approach and are applicable to a large class of networks in which the computations can be described by means of matrix and vector operations. A detailed characterization of the target machine is provided. Two mappings are presented. The first is designed for a processor array consisting of a very large number of small processing units. The neurons and the nonzero synaptic weights are assigned to the processors in a predetermined order, one per processor. The data transfers between processors containing neurons and weights are implemented using a novel routing algorithm. The second mapping is designed for the data array of size N*N and a smaller processor array of size P*P, P>>N, i.e., it addresses the partitioned case. These mappings are applicable to most of the mesh-connected single-instruction-multiple-data (SIMD) machines.</p>
algorithmic mapping; matrix operations; neural network models; parallel SIMD machines; programmable massively parallel computers; graph theoretic approach; vector operations; processor array; nonzero synaptic weights; data transfers; neurons; routing algorithm; graph theory; neural nets; parallel processing.
W.-M. Lin, V.K. Prasanna, K.W. Przytula, "Algorithmic mapping of neural network Models onto Parallel SIMD Machines", IEEE Transactions on Computers, vol. 40, no. , pp. 1390-1401, December 1991, doi:10.1109/12.106224