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<p>The authors present a novel approach to the test generation problem for a more general class of two-dimensional iterative logic arrays (ILAs) than considered by previous researchers. For certain ILAs it is possible to find a test set whose size remains fixed irrespective of the size of the ILA, while for others it varies with array size. Given an arbitrary ILA cell truth table and a cell interconnection structure, the goal is to determine if a fixed-size test can be found. If not, then a test set whose size grows as slowly as possible with the size of the array should be found. The authors propose a new model, called the n-cube of cell states model, for representing the cell truth table and interconnection structure. The test generation problem is shown to be related to certain properties of cycles in a set of graphs obtained from this model. By careful analysis of these cycles, efficient testing schedules can be obtained. The proposed technique can be applied to unilateral as well as regular bilateral ILAs in which the bilateral direction of signal flow are restricted to lie along the horizontal axis.</p>
N-cube; cell states model; test generation; two-dimensional iterative logic arrays; test set; ILA cell truth table; cell interconnection structure; graphs; bilateral direction; signal flow; horizontal axis; automatic testing; integrated circuit testing; logic arrays; logic testing.

A. Chatterjee and J. Abraham, "Test Generation for Iterative Logic Arrays Based on an N-Cube of Cell States Model," in IEEE Transactions on Computers, vol. 40, no. , pp. 1133-1148, 1991.
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