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<p>An extension of a previous approach to fault detection and C-testability of orthogonal iterative arrays is presented. The state transition table of a basic cell is analyzed. Five new states are added to it. It is proved that even though the number of additional states in the proposed approach is greater than previous approaches, (five states compared to four), the required number of test vectors is considerably reduced (by a factor of approximately 4/9). An approach to implement the proposed C-testability approach into logic design is also presented. Complexity of this implementation is analyzed.</p>
design complexity; C-testable VLSI arrays; fault detection; orthogonal iterative arrays; state transition table; test vectors; logic design; logic arrays; logic testing; VLSI.
F. Lombardi, W. Huang, "Fault Detection and Design Complexity in C-Testable VLSI Arrays", IEEE Transactions on Computers, vol. 39, no. , pp. 1477-1481, December 1990, doi:10.1109/12.61070
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