Issue No. 11 - November (1990 vol. 39)
DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/12.61047
<p>Conventional schemes for fast multiplication accumulate the partial products in redundant form (carry-save or signed-digit) and convert the result to conventional representation in the last step. This step requires a carry-propagate adder which is comparatively slow and occupies a significant area of the chip in a VLSI implementation. A report is presented on a multiplication scheme (left-to-right, carry-free, LRCF) that does not require this carry-propagate step. The LRCF scheme performs the multiplication most-significant bit first and produces a conventional sign-and-magnitude product (most significant n bits) by means of an on-the-fly conversion. The resulting implementation is fast and regular and is very well suited for VLSI. The LRCF scheme for general radix r and a radix-4 signed-digit implementation are presented.</p>
fast multiplication; carry-propagate adder; LRCF scheme; general radix r; radix-4 signed-digit implementation; digital arithmetic.
M.D. Ercegovac, T. Lang, "Fast Multiplication Without Carry-Propagate Addition", IEEE Transactions on Computers, vol. 39, no. , pp. 1385-1390, November 1990, doi:10.1109/12.61047