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<p>A multibit recoding algorithm for signed two's complement binary numbers is presented and proved. In general, a k+1-bit recoding will result in a signed-digit (SD) representation of the binary number in radix 2/sup k/, using digits -2/sup k-1/ to +2/sup k-1/ including 0. It is shown that a correct SD representation of the original number is obtained by scanning K+1-tuples (k≤1) with one bit overlapping between adjacent groups. Recording of binary numbers has been used in computer arithmetic with 3-bit recoding being the dominant scheme. With the emergence of very high speed adders, hardware parallel multipliers using multibit recoding with k<2 are feasible, with the potential of improving both the performance and the hardware requirements. A parallel hardware multiplier based on the specific case of 5-bit recoding is proposed. Extensions beyond 5-bit recoding for multiplier design are studied for their performance and hardware requirements. Other issues relating to multiplier design, such as multiplication by a fixed or controlled coefficient, are also discussed in the light of multibit recoding.</p>
signed-digit representation; fixed coefficient multiplication; controlled coefficient multiplication; multibit recoding algorithm; signed two's complement binary numbers; radix 2/sup k/; computer arithmetic; very high speed adders; hardware parallel multipliers; 5-bit recoding; performance; digital arithmetic; multiplying circuits.
H. Sam, A. Gupta, "A Generalized Multibit Recoding of Two's Complement Binary Numbers and its Proof with Application in Multiplier Implementations", IEEE Transactions on Computers, vol. 39, no. , pp. 1006-1015, August 1990, doi:10.1109/12.57039
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