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<p>A synchronizer timing model, called the jitter model, which has general application to metastable reliability analysis, is proposed and analyzed. The jitter model is applied to show that redundancy cannot improve the metastable reliability of synchronizers, contradicting previous work by A. El-Amawy. The jitter model extends previous synchronizer input timing models by incorporating the effects of circuit noise. The circuit noise translates into jitter or random time displacement of a previously proposed deterministic aperture mode. The jitter model is supported by simulation, circuit analysis, and experimental work. The results of a SPICE simulation of a CMOS D-type flip-flop are presented. An experimental bistable device is constructed to examine the behavior of synchronizers with noise. Statistical results obtained from the experimental bistable device support the jitter model for metastability. The sensitivity of metastable reliability of redundant synchronizers to modeling assumptions is highlighted.</p>
jitter model; metastability; redundant synchronizers; timing model; reliability analysis; circuit noise; simulation; circuit analysis; SPICE; CMOS D-type flip-flop; bistable device; circuit analysis computing; CMOS integrated circuits; flip-flops; integrated logic circuits.

L. Kleeman, "The Jitter Model for Metastability and its Application to Redundant Synchronizers," in IEEE Transactions on Computers, vol. 39, no. , pp. 930-942, 1990.
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