Issue No. 03 - March (1990 vol. 39)

ISSN: 0018-9340

pp: 400-404

DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/12.48871

ABSTRACT

<p>An algorithm with worst case time complexity O(log/sup 2/N) in two dimensions and O(m/sup 1/2/log N) in three dimensions with N input points and m as the number of tetrahedra in triangulation is given. Its AT/sup 2/ VLSI complexity on Thompson's logarithmic delay model, (1983) is O(N/sup 2/log/sup 6/N) in two dimensions and O(m/sup 2/Nlog/sup 4/ N) in three dimensions.</p>

INDEX TERMS

VLSI parallel algorithm; Delaunay triangulation; orthogonal tree network; worst case time complexity; tetrahedra; logarithmic delay model; computational complexity; parallel algorithms; trees (mathematics).

CITATION

P.C.P. Bhatt, V.C. Prasad, F. Saxena, "Efficient VLSI Parallel Algorithm for Delaunay Triangulation on Orthogonal Tree Network in Two and Three Dimensions",

*IEEE Transactions on Computers*, vol. 39, no. , pp. 400-404, March 1990, doi:10.1109/12.48871