Instruction Issue Logic for High-Performance, Interruptible, Multiple Functional Unit, Pipelined Computers
Issue No.03 - March (1990 vol.39)
DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/12.48865
<p>The problems of data dependency resolution and precise interrupt implementation in pipelined processors are combined. A design for a hardware mechanism that resolves dependencies dynamically and, at the same time, guarantees precise interrupts is presented. Simulation studies show that by resolving dependencies the proposed mechanism is able to obtain a significant speedup over a simple instruction issue mechanism as well as implement precise interrupts.</p>
pipelined computers; data dependency resolution; precise interrupt implementation; pipelined processors; interrupts; instruction issue mechanism; interrupts; parallel architectures; pipeline processing.
G.S. Sohi, "Instruction Issue Logic for High-Performance, Interruptible, Multiple Functional Unit, Pipelined Computers", IEEE Transactions on Computers, vol.39, no. 3, pp. 349-359, March 1990, doi:10.1109/12.48865