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<p>The problems of data dependency resolution and precise interrupt implementation in pipelined processors are combined. A design for a hardware mechanism that resolves dependencies dynamically and, at the same time, guarantees precise interrupts is presented. Simulation studies show that by resolving dependencies the proposed mechanism is able to obtain a significant speedup over a simple instruction issue mechanism as well as implement precise interrupts.</p>
pipelined computers; data dependency resolution; precise interrupt implementation; pipelined processors; interrupts; instruction issue mechanism; interrupts; parallel architectures; pipeline processing.

G. Sohi, "Instruction Issue Logic for High-Performance, Interruptible, Multiple Functional Unit, Pipelined Computers," in IEEE Transactions on Computers, vol. 39, no. , pp. 349-359, 1990.
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