Issue No. 02 - February (1990 vol. 39)
DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/12.45214
<p>A linear systolic array with fault-tolerant capabilities is described. Fault tolerance is achieved by using triple time redundancy. The array is capable of undergoing reconfiguration and can operate in a gracefully degradable mode. The concept of algorithm remapping on degraded (smaller) arrays is integrated with that of graceful degradation to obtain a general fault-tolerance technique. A new technique for restructuring algorithms and executing them on a degraded array is discussed. The requisite modifications of the interconnection, switching, and control structures to achieve fault tolerance are discussed. Reliability analysis of the system is carried out, and the reliability is compared to that of nonredundant systolic arrays. Finally, the average performance of the system, with running time and throughput as performance metrics, is estimated.</p>
reliability analysis; linear systolic arrays; fault-tolerant capabilities; triple time redundancy; reconfiguration; gracefully degradable mode; interconnection; switching; control structures; running time; throughput; performance metrics; cellular arrays; fault tolerant computing; logic testing.
M.A. Breuer, A. Majumdar, C.S. Raghavendra, "Fault Tolerance in Linear Systolic Arrays Using Time Redundancy", IEEE Transactions on Computers, vol. 39, no. , pp. 269-276, February 1990, doi:10.1109/12.45214