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Issue No. 01 - January (1990 vol. 39)
ISSN: 0018-9340
pp: 141-145
<p>A hardware accelerator for the maze routing problem is developed. This accelerator consists of three three-stage pipelines. Banked memory is used to avoid memory read/write conflicts and obtain maximum efficiency. The design is compared to other proposed designs. Unlike other proposed hardware solutions for this problem, this design does not require an increase in the number of processors as the problem size increases.</p>
banked memory; hardware accelerator; maze routing; three-stage pipelines; circuit layout CAD.

Y. El-Ziq, Y. Won and S. Sahni, "A Hardware Accelerator for Maze Routing," in IEEE Transactions on Computers, vol. 39, no. , pp. 141-145, 1990.
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