Issue No.09 - September (1989 vol.38)
DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/12.29475
VLSI designs for Galois field multipliers, which are central in many encoding and decoding procedures for error-detecting and error-correcting codes, are presented. An AT/sup 2/-optimal Galois-field multiplier based on AT/sup 2/-optimal integer multipliers for a synchronous VLSI model is exhibited. Galois field multiplication is done in two steps. First two polynomials (of degree n-1) over Z/su
error detection codes; AT/sup 2/-optimal Galois field multiplier; VLSI; encoding; decoding; error-correcting codes; integer multipliers; polynomials; discrete Fourier transform; open problems; decoding; digital arithmetic; encoding; multiplying circuits; VLSI.
M. Furer, K. Mehlhorn, "AT/sup 2/-Optimal Galois Field Multiplier for VLSI", IEEE Transactions on Computers, vol.38, no. 9, pp. 1333-1336, September 1989, doi:10.1109/12.29475