Issue No. 09 - September (1989 vol. 38)
DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/12.29466
The use of two parallel architectures, a single-instruction-stream, multiple-data-stream (SIMD) machine and a VLSI processor array, to implement an isolated word recognition system is examined. SIMD and VLSI processor array algorithms are written for each of the components of the recognition system. The component parallel algorithms are simulated along with two complete recognition systems, one
word recognition system; parallel architectures; SIMD; VLSI processor array; parallel algorithms; simulations; 8-MHz MC68000; 12-MHz Intel 8051; digital simulation; parallel algorithms; parallel architectures; speech recognition.
L.H. Jamieson, M.A. Yoder, "Simulation of a Word Recognition System on Two Parallel Architectures", IEEE Transactions on Computers, vol. 38, no. , pp. 1269-1284, September 1989, doi:10.1109/12.29466