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Analytical models are developed for seven existing cache protocols, namely, Write-Once, Write-Through, Synapse, Berkeley, Illinois, Firefly, and Dragon. The protocols are implemented on a multiprocessor with a packet-switched shared bus. The models are based on queuing networks that consist of both open and closed classes of customers. The models incorporate the requests for invalidation signal
analytical models; cache coherence protocols; packet-switched multiprocessor; Write-Once; Write-Through; Synapse; Berkeley; Illinois; Firefly; Dragon; queuing networks; invalidation signals; write-back; mean value analysis; multiprocessing systems; packet switching; protocols; queueing theory.
L.N. Bhuyan, B.-C. Liu, Q. Yang, "Analysis and Comparison of Cache Coherence Protocols for a Packet-Switched Multiprocessor", IEEE Transactions on Computers, vol. 38, no. , pp. 1143-1153, August 1989, doi:10.1109/12.30868
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