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The authors present an efficient scheme for the layout of large binary-tree architectures by embedding the complete binary tree in a two-dimensional array of processing elements. Their scheme utilizes virtually 100% of the processing elements in the array as computing elements; it also shows substantial improvements in propagation delay and maximum edge length over H-tree layouts. They shown th
large binary tree architectures; VLSI; WSI; layout; two-dimensional array; processing elements; propagation delay; maximum edge length; H-tree layouts; fault-tolerant designs; circuit layout CAD; trees (mathematics); VLSI.
A.D. Singh, H.Y. Youn, "On Implementing Large Binary Tree Architectures in VLSI and WSI", IEEE Transactions on Computers, vol. 38, no. , pp. 526-537, April 1989, doi:10.1109/12.21145
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