The Community for Technology Leaders
Green Image
A simple mapping technique is developed to design systolic arrays with limited I/O capability. The technique is used to improve systolic algorithms for some matrix computations on linearly connected arrays of PEs (processor elements) with constant I/O bandwidth. The important features of these designs are modularity with constant hardware in each PE, few control lines, simple data-input/output
linear systolic arrays; algorithms; fault-tolerant systolic arrays; mapping technique; matrix computations; linearly connected arrays; processor elements; VLSI model; propagation delay; Diogenes methodology; cellular arrays; fault tolerant computing.

Y. Tsai and V. Kumar, "On Mapping Algorithms to Linear and Fault-Tolerant Systolic Arrays," in IEEE Transactions on Computers, vol. 38, no. , pp. 470-478, 1989.
87 ms
(Ver 3.3 (11022016))