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An architecture is proposed for multimegabit dynamic RAMs (random-access memories) that achieves higher testability and performance than the conventional four-quadrant RAMs. Applying the principle of divide and conquer, the RAM is partitioned into modules, each appearing as the leaf node of a binary interconnect network. Such a network carries the address/data/control bus, permitting the nodes
TRAM; design methodology; high-performance; multimegabit dynamic RAMs; testability; performance; yield; reliability; integrated memory circuits; random-access storage.
N.T. Jarwala, D.K. Pradhan, "TRAM: A Design Methodology for High-Performance, Easily Testable, Multimegabit RAMs", IEEE Transactions on Computers, vol. 37, no. , pp. 1235-1250, October 1988, doi:10.1109/12.5985
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