The Community for Technology Leaders
Green Image
Issue No. 06 - June (1988 vol. 37)
ISSN: 0018-9340
pp: 749-751
A bit-serial systolic array has been developed to computer multiplications over GF(2/sup m/). In contrast to a previously designed systolic multiplier, this algorithm allows the input elements to center a linear systolic array in the same order, and the system only requires one control signal.
bit-serial systolic multiplier; linear systolic array; cellular arrays; logic design; VLSI.

B. Zhou, "A New Bit-Serial Systolic Multiplier Over GF(2/sup m/)," in IEEE Transactions on Computers, vol. 37, no. , pp. 749-751, 1988.
86 ms
(Ver 3.3 (11022016))