Issue No.05 - May (1988 vol.37)
DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/12.4615
A fault-tolerant systolic sorter design is proposed. An algorithm-based fault tolerance is achieved by testing the invariants of a systolic sorter during normal operation. Transient and permanent computation errors can be detected by using error-checking code and some redundant cells. A block with a single faulty cell can be located. Small hardware overhead and negligible time overhead are show
reconfiguration; VLSI sorter; fault-tolerant systolic sorter; algorithm-based fault tolerance; testing; invariants; permanent computation errors; error-checking code; redundant cells; single faulty cell; hardware overhead; time overhead; offline fault-testing; permanent stuck-at faults; automatic testing; cellular arrays; digital integrated circuits; error detection codes; fault tolerant computing; integrated circuit testing; redundancy; sorting.
Y.-H. Choi, M. Malek, "A Fault-Tolerant Systolic Sorter", IEEE Transactions on Computers, vol.37, no. 5, pp. 621-624, May 1988, doi:10.1109/12.4615