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ABSTRACT
The performance and cost of a modulo-3 residue code checker that has been attached to a pipelined serial multiplier to provide a concurrent self-test capability are considered. Analytical results are derived for error detection coverage and minimum error latency; these quantities are observed to be in agreement with simulation results obtained by using ISPS, a register-transfer language. The re
INDEX TERMS
built in test; modulo-3 residue code checker; pipelined serial multiplier; concurrent self-test; error detection coverage; minimum error latency; multiplier input operands; 4- mu m NMOS; standard cell design; automatic testing; digital arithmetic; error detection; field effect integrated circuits; integrated circuit testing; multiplying circuits; performance evaluation; pipeline processing.
CITATION
J.W. Watterson, J.J. Hallenbeck, "Modulo 3 Residue Checker: New Results on Performance and Cost", IEEE Transactions on Computers, vol. 37, no. , pp. 608-612, May 1988, doi:10.1109/12.4612
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