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Five solutions to the precise interrupt problem in pipelined processors are described and evaluated. An interrupt is precise if the saved process state corresponds to a sequential model of program execution in which one instruction completes before the next begins. In a pipelined processor, precise interrupts are difficult to implement because an instruction may be initiated before its predeces
precise recovery; pipelined processors; precise interrupt problem; saved process state; sequential model of program execution; architectural order; parallel pipeline structure; Cray-1S scalar architecture; performance degradation; interrupts; parallel architectures; performance evaluation; pipeline processing; system recovery.
J.E. Smith, A.R. Pleszkun, "Implementing Precise Interrupts in Pipelined Processors", IEEE Transactions on Computers, vol. 37, no. , pp. 562-573, May 1988, doi:10.1109/12.4607
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