Issue No. 04 - April (1988 vol. 37)
DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/12.2192
A reconfiguration scheme is presented that is suitable for both yield and reliability enhancement of large-area VLSI implementations of binary tree architectures. The approach proposed makes use of partially global redundancy to allow clustered effects to be tolerated. The binary tree is cut a few levels above the leaves to form an upper subtree and many lower subtrees, with spare processors be
reconfiguration scheme; yield enhancement; large area binary tree architectures; reliability enhancement; VLSI; partially global redundancy; programmable switches; computer architecture; fault tolerant computing; trees (mathematics).
M.C. Howells, V.K. Agarwal, "A Reconfiguration Scheme for Yield Enhancement of Large Area Binary Tree Architectures", IEEE Transactions on Computers, vol. 37, no. , pp. 463-468, April 1988, doi:10.1109/12.2192