The Community for Technology Leaders
Green Image
Issue No. 03 - March (1988 vol. 37)
ISSN: 0018-9340
pp: 362-368
In verification of n-bit CMOS memories it is usual to supply a test address sequence having n2/sup /n transitions, one for each ordered pair of n-bit words which differ in a single bit. From an inductive definition of a sequence with these properties, a succession of algorithms yielding the logic circuit of a next-state generator for the sequence is developed. Proving these algorithms equivalen
transition sequence generator; RAM fault detection; n-bit CMOS memories; test address sequence; ordered pair; logic circuit; next-state generator; CMOS integrated circuits; integrated circuit testing; integrated memory circuits; random-access storage.

E. Regener, "A Transition Sequence Generator for RAM Fault Detection," in IEEE Transactions on Computers, vol. 37, no. , pp. 362-368, 1988.
89 ms
(Ver 3.3 (11022016))