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The design of a special-purpose CMOS processor for digital signal processing is described. A high degree of processing concurrency is achieved through the use of two modified pipelined architectures in parallel. Each pipeline section is connected to a bus for maximum flexibility in accessing any stage in the pipeline. Each pipeline section can be dynamically configured under microprogram contro
multiple-access pipeline architecture; digital signal processing; CMOS processor; processing concurrency; microprogram control; floating-point data; arithmetic logic unit; computerised signal processing; digital arithmetic; parallel architectures.

F. El Guibaly and B. McKinney, "A Multiple-Access Pipeline Architecture for Digital Signal Processing," in IEEE Transactions on Computers, vol. 37, no. , pp. 283-290, 1988.
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