The Community for Technology Leaders
Green Image
Issue No. 03 - March (1988 vol. 37)
ISSN: 0018-9340
pp: 274-282
A parallel multiplier design based on the five-counter cell is discussed. A design optimization for the performance in speed is proposed at the logic design level which is developed into an MOS circuit design. The comparison of the five-counter cell design and the full adder cell design reveals that the proposed design is most useful with pass gate logic and results in high-speed multiplication
single chip parallel multiplier; MOS technology; five-counter cell; design optimization; logic design level; full adder cell design; field effect integrated circuits; integrated logic circuits; logic design; multiplying circuits.

K. Chu and S. Nakamura, "A Single Chip Parallel Multiplier by MOS Technology," in IEEE Transactions on Computers, vol. 37, no. , pp. 274-282, 1988.
99 ms
(Ver 3.3 (11022016))