Issue No. 03 - March (1988 vol. 37)
DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/12.2164
A parallel multiplier design based on the five-counter cell is discussed. A design optimization for the performance in speed is proposed at the logic design level which is developed into an MOS circuit design. The comparison of the five-counter cell design and the full adder cell design reveals that the proposed design is most useful with pass gate logic and results in high-speed multiplication
single chip parallel multiplier; MOS technology; five-counter cell; design optimization; logic design level; full adder cell design; field effect integrated circuits; integrated logic circuits; logic design; multiplying circuits.
K.-Y. Chu, S. Nakamura, "A Single Chip Parallel Multiplier by MOS Technology", IEEE Transactions on Computers, vol. 37, no. , pp. 274-282, March 1988, doi:10.1109/12.2164