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Issue No. 03 - March (1988 vol. 37)
ISSN: 0018-9340
pp: 258-265
A design technique for totally self-checking (TSC) error correcting/detection (C/D) circuits of single error correcting, double error detection (SEC/DED) codes is described. The structure of these circuits achieves concurrent fault detection and location under normal input conditions. A separate internal fault indication is provided. This improves the reliability, maintainability, and availabil
error correction circuits; error detection circuits; totally self-checking; single error correcting; double error detection; codes; concurrent fault detection; reliability; maintainability; availability; fault-tolerant system; error locators; automatic testing; error correction codes; error detection codes; fault tolerant computing; logic testing.
N. Gaitanis, "The Design of TSC Error C/D Circuits for SEC/DED Codes", IEEE Transactions on Computers, vol. 37, no. , pp. 258-265, March 1988, doi:10.1109/12.2162
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