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Issue No. 02 - February (1988 vol. 37)
ISSN: 0018-9340
pp: 190-200
The architecture and performance of a 20-bit arithmetic processor based on the logarithmic number system (LNS) is described. The processor performed LNS multiplication and division rapidly and with a low hardware complexity. Addition and subtraction in the LNS require the support of a table lookup unit. A scheme is proposed to minimize this complexity using a partitioned memory (ROM) and a PLA
logarithmic number system processor; architecture; arithmetic processor; table lookup; partitioned memory; ROM; PLA; performance evaluation; integrated Schottky logic; 20 bit; computer architecture; digital arithmetic; field effect integrated circuits; microprocessor chips; performance evaluation; satellite computers; table lookup.
F.J. Taylor, R. Gill, J. Radke, J. Joseph, "A 20 Bit Logarithmic Number System Processor", IEEE Transactions on Computers, vol. 37, no. , pp. 190-200, February 1988, doi:10.1109/12.2148
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