The Community for Technology Leaders
Green Image
Issue No. 10 - October (1987 vol. 36)
ISSN: 0018-9340
pp: 1243-1247
null I-Chen wu , Department of Computer Science, Carnegie-Mellon University
Based on the modified Booth's algorithm, a fast 1-D serial- parallel systolic multiplier is designed for multiplying two's complement numbers. The circuit with countercurrent data flow pattern accepts the multiplicand serially, the multiplier in parallel, and outputs the product serially. It requires a complementer and N/2 cells, each of which contains a ripple-carry adder and some gates, where N is restricted to even. The number of clocks required to multiply an n-bit (n = N) multiplier and an m-bit multiplicand is equal to n + m - 1, and independent of the circuit size N.
VLSI, Countercurrent data flow pattern, five-level multiplexer, five-level recorder, modified Booth's Algorithm, systolic multilier, two's complement

n. I-Chen wu, "A Fast 1-D Serial-Parallel Systolic Multiplier," in IEEE Transactions on Computers, vol. 36, no. , pp. 1243-1247, 1987.
82 ms
(Ver 3.3 (11022016))