Issue No. 10 - October (1987 vol. 36)
G.R. Redinbo , Departrnent of Electrical and Computer Engineering/ Computer Science, University of California
Digital filtering architectures that simultaneously offer advantages for VLSI fabrication and contain distributed error control are presented. Such structures require parallelism as well as inherent error- control capabilities because VLSI implementations are susceptible to temporary and intermittent hardware errors. The filtering convolution operation is similar to the formation of cyclicerror-correcting codes so that fault-tolerant systems employing finite field arithmetic may be designed containing such codes imbedded directly in the architecture. The interconnection of such systems produces a fault-tolerant system. In addition, the subsystems possess a common design structure which is easily customized to the particular field required, an attractive feature for yield enhancement. Straightforward realizations depending on parallel algebraic decompositions are studied, introducing the locations for fault tolerance and the role of cyclic codes.
VLSI, Chinese Remainder Theorem, cyclic codes, digital filtering, error-correcting codes, fault-tolerant computing, finite fields, residue arithmetic
G.R. Redinbo, "Finite Field Fault-Tolerant Digital Filtering Architectures", IEEE Transactions on Computers, vol. 36, no. , pp. 1236-1242, October 1987, doi:10.1109/TC.1987.1676864