A Construction Method of High-Speed Decoders Using ROM's for Bose?Chaudhuri?Hocquenghem and Reed?Solomon Codes
Issue No. 10 - October (1987 vol. 36)
H. Okano , Department of Information and Electronics, Tokuyama Technical College
In this paper, some efficient methods of solving equations over Galois field GF(2m) are proposed. Using these algorithms, decoders for triple-and quadruple-error-correcting Bose?Chaudhuri?Hocquenghem (BCH) codes are shown. More- over, we propose a new method of making high-speed decoders for double-error-correcting/triple-error-detecting BCH or Reed- Solomon (RS) codes by adding a simple error-identifying circuit to a decoder for double-error-correcting codes. By incorporating ROM's (read only memory) in a decoder, the complex logic circuits are eliminated and then we can easily construct a high- speed decoder. We evaluate the complexity of the decoders and show that each of them can be accommodated in a single chip LSI.
solution of equations, BCH decoders, error-correcting codes, Galois fields, LSI, read-only memories, Reed-Solomon decoders
H. Imai and H. Okano, "A Construction Method of High-Speed Decoders Using ROM's for Bose?Chaudhuri?Hocquenghem and Reed?Solomon Codes," in IEEE Transactions on Computers, vol. 36, no. , pp. 1165-1171, 1987.