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Issue No. 03 - March (1987 vol. 36)
ISSN: 0018-9340
pp: 369-373
R. Treuer , Department of Electrical Engineering, McGill University
This correspondence presents a new built-in self-test design for PLA's, that has a lower area overhead and higher multiple fault coverage (of three types of faults: crosspoint, stuck, and bridging) than any existing design. This new design uses function independent test input patterns (which are generated on chip), compresses the output responses into a function independent string of parity bits (whose fault-free expected values are generated on-line with a simple circuit), and detects all siqgle faults and more than ( 1 --2(m+2n) of all multiple faults where m and n represent the number of product terms and input variables, respectively.
VLSI design, Built-in self test (BIST), fault coverage, fault models, output response compression, parity bits, programmable logic array (PLA), test pattern generation
V.K. Agarwal, R. Treuer, H. Fujiwara, "A New Built-In Self-Test Design for PLA's with Hligh Fault Coverage and Low Overhead", IEEE Transactions on Computers, vol. 36, no. , pp. 369-373, March 1987, doi:10.1109/TC.1987.1676911
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