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Issue No. 03 - March (1987 vol. 36)
ISSN: 0018-9340
pp: 344-355
I. Koren , Department of Electrical and Computer Engineering, University of Massachusetts
The incorporation of different forms of redundancy has been recently proposed for various VLSI and WSI designs. These include regular architectures, built by interconnecting a large number of a few types of system elements on a single chip or wafer. The motivation for introducing fault-tolerance (redundancy) into these architectures is two-fold: yield enhancement and performance (like computational availability) improvement.
yield, Computational availability, fault tolerance, redundancy, reliability, VLSI designs, wafer-scale integration
D.K. Pradhan, I. Koren, "Modeling the Effect of Redundancy on Yield and Performance of VLSI Systems", IEEE Transactions on Computers, vol. 36, no. , pp. 344-355, March 1987, doi:10.1109/TC.1987.1676906
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