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Issue No. 02 - February (1987 vol. 36)
ISSN: 0018-9340
pp: 250-252
null Wenlong Zang , Department of Electrical and Computer Engineering, University of Massachusetts
A new design procedure is described for constructing rate 1/2 and rate 2/3 majority logical decodable burst error-correcting codes. The rate 1/2 codes are closely related to the codes of Srinivasan [1].
VLSI, Burst error codes, coding, decoding, ECC codes, error control, fault tolerance, majority logic codes
null Wenlong Zang, J.K. Wolf, "Rate 1/2 and 2/3 Majority Logic Decodable Binary Burst Error-Correcting Codes", IEEE Transactions on Computers, vol. 36, no. , pp. 250-252, February 1987, doi:10.1109/TC.1987.1676891
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