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A well-known technique for providing tolerance against single hardware component failures is triplication of the component, called triple modular redundancy (TMR). In this paper a component is taken to be a processor-memory configuration where the memory is organized in a bit-sliced way. If voting is performed bitwise in an orthodox TMR configuration consisting of three of these components, failure of a complete component or failure of bit-slices not on corresponding positions in the memories can be tolerated. We present a TMR technique, not using more redundancy than orthodox TMR, that can tolerate the failure of arbitrary bit-slices (including those on corresponding positions) up to a certain amount. Additionally it can tolerate the failure of arbitrary bit-slices up to a certain amount whenever one component is known to be malfunctioning or whenever one component is disabled. This generalized TMR technique is described for processor-memory configurations processing 4-, 8-, and 16-bit words, respectively.
triple modular redundancy, Combined symbol and bit error detection/ correction, error-correcting codes, fault-masking/ -correction techniques, Galois fields, hardware fault-tolerant design methodology
W.J. Van Gils, "A Triple Modular Redundancy Technique Providing Multiple-Bit Error Protection Without Using Extra Redundancy", IEEE Transactions on Computers, vol. 35, no. , pp. 623-631, July 1986, doi:10.1109/TC.1986.1676803
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