The Community for Technology Leaders
Green Image
Issue No. 05 - May (1986 vol. 35)
ISSN: 0018-9340
pp: 462-475
V. Ramachandran , Coordinated Science Laboratory, University of Illinois
We present algorithms and time complexity results for MOS switch-level simulation with particular reference to race detection. Under the switching model used in classical (Boolean) switching theory, we derive a linear-time race detection algorithm for switch-level circuits that have no feedback within a clock phase, and have unit fan-out. We show that the problem becomes NP-complete if fan-out of two or more is allowed. We Also relate this result to others that have recently been reported, using a different switching model.
switch-level simulation, Computer-aided design tools, graph algorithms, linear-time simulation, MOS VLSI, NP-completeness, race detection

V. Ramachandran, "Algorithmic Aspects of MOS VLSI Switch-Level Simulation with Race Detection," in IEEE Transactions on Computers, vol. 35, no. , pp. 462-475, 1986.
83 ms
(Ver 3.3 (11022016))