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TABLE OF CONTENTS
Issue No. 04 - April (vol. 35)
ISSN: 0018-9340
Papers

IEEE Computer Society (PDF)

pp. c2

Editor's Notice (PDF)

pp. 285

Fault-Tolerant Computing: An Introduction (PDF)

S.B. Akers , Dep. Elec. & Comput. Eng. University of Massachusetts
pp. 285-287

List of Referees (PDF)

pp. 287

Robust Storage Structures for Crash Recovery (Abstract)

D.J. Taylor , Department of Computer Science, University of Waterloo
pp. 288-295

Bounds on Algorithm-Based Fault Tolerance in Multiple Processor Systems (PDF)

P. Banerjee , Department of Electrical and Computer Engineering and the Coordinated Science Laboratory, University of Illinois
pp. 296-306

Fault-Tolerant Multiprocessors with Redundant-Path Interconnection Networks (PDF)

C.S. Raghavendra , Department of Electrical Engineering-Systems, University of Southern Califomia
pp. 307-316

Accumulator Compression Testing (PDF)

N.R. Saxena , Hewlett Packard
pp. 317-321

Provably Conservative Approximations to Complex Reliability Models (Abstract)

M. Smotherman , Department of Computer Science, Clemson University
pp. 333-338

(N, K) Concept Fault Tolerance (Abstract)

T. Krol , Philips Research Laboratories
pp. 339-349

Burst Unidirectional Error-Detecting Codes (Abstract)

B. Bose , Department of Computer Science, Oregon State University
pp. 350-353

A Fault-Tolerant Modular Architecture for Binary Trees (Abstract)

A.S. Mahmudul Hassan , Department of Electrical Engineering, McGill University
pp. 356-361

Test Schedules for VLSI Circuits Having Built-In Test Hardware (Abstract)

M.S. Abadir , Department of Electrical Engineering, University of Southern Califomia
pp. 361-367

Condensed Linear Feedback Shift Register (LFSR) Testing?A Pseudoexhaustive Test Technique (PDF)

null Laung-Terng Wang , Center for Reliable Computing, Computer Systems Laboratory, Departments of Electrical Engineering and Computer Science, Stanford University
pp. 367-370

Measurement and Application of Fault Latency (Abstract)

K.G. Shin , Division of Computer Science and Engineering, Department of Electrical Engineering and Computer Science, University of Michigan
pp. 370-375

Functional Test Generation for Digital Circuits Described Using Binary Decision Diagrams (Abstract)

M.S. Abadir , Department of Electrical Engineering?Systems, University of Southern California
pp. 375-379

An Alternative to Scan Design Methods for Sequential Machines (Abstract)

K.K. Saluja , Department of Electrical and Computer Engineering, University of Wisconsin
pp. 384-388

Information for Authors (PDF)

pp. 388
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