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Issue No. 04 - April (1986 vol. 35)
ISSN: 0018-9340
pp: 375-379
M.S. Abadir , Department of Electrical Engineering?Systems, University of Southern California
This correspondence presents a test generation methodology for VLSI circuits described at the functional level. A VLSI circuit is modeled as a network of functional modules such as registers, adders, RAM's, and MUX's. The functions of the individual modules are described using binary decision diagrams. A functional fault model is developed independent of the implementation details of the circuit. A generalized D algorithm is proposed for generating tests to detect functional as well as gate-level faults. Algorithms which perform fault excitation, implication, D propagation, and line justification on the functional modules are also described.
functional test generation, Binary decision diagrams, D algorithm, fault model, fault detection, functional faults

H. Reghbati and M. Abadir, "Functional Test Generation for Digital Circuits Described Using Binary Decision Diagrams," in IEEE Transactions on Computers, vol. 35, no. , pp. 375-379, 1986.
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