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Issue No. 01 - January (vol. 35)
ISSN: 0018-9340

IEEE Computer Society (PDF)

pp. c2

Partitioning and Mapping Algorithms into Fixed Size Systolic Arrays (PDF)

D.I. Moldovan , Department of Electrical Engineering?Systems, University of Southern Califomia
pp. 1-12

Testability Conditions for Bilateral Arrays of Combinational Cells (Abstract)

A. Vergis , Department of Computer Science, University of Minnesota
pp. 13-22

DFSP: A Data Flow Signal Processor (Abstract)

I. Hartimo , Department of Technical Physics, Helsinki University of Technology
pp. 23-33

A Heuristic for Suffix Solutions (Abstract)

A. Bilgory , Department of Electrical Engineering, Technion?Israel Institute of Technology
pp. 34-42

An Enhanced Approximation by Pair-Wise Analysis of Servers for Time Delay Distributions in Queueing Networks (Abstract)

P.G. Harrison , Department of Computing, Imperial College of Science and Technology, University of London
pp. 54-61

The Bidirectional Double Latch (BDDL) (Abstract)

J. Savir , IBM Data Systems Division
pp. 65-66

Asynchronous Modular Arbiter (Abstract)

J. Calvo , Departamento de Electricidad y Electr?nica, F. Fisica, Universidad de Sevilla
pp. 67-70

Deductive Fault Simulation of Internal Faults of Inverter-Free Circuits and Programmable Logic Arrays (Abstract)

F. Ozguner , Department of Electrical Engineering, The Ohio State University
pp. 70-73

Systolic Algorithnis for Local Operations on Images (Abstract)

C. Guerra , Department of Computer Science, Purdue University
pp. 73-77

The Influence of Masking Phenomenon on Coverage Capability of Single Fault Test Sets in PLA's (Abstract)

J. Rajski , Department of Electrical Engineering, McGill University
pp. 81-85

On System Diagnosability in the Presence of Hybrid Faults (Abstract)

A. Sengupta , Department of Computer Science, University of South Carolina
pp. 90-93

Comments on "The Diogenes Approach to Testable Fault-Tolerant Arrays of Processors" (PDF)

I. Koren , Department of Electrical Engineering, Technion?Israel Institute of Technology
pp. 93

Author's Reply<sup>2</sup> (PDF)

A.L. Rosenberg , Department of Computer Science, Duke University
pp. 93-94

Correction to "Fault-Tolerant Multiprocessor Link and Bus Architectures" (PDF)

D.K. Pradhan , Department of Electrical and Computer Engineering, University of Massachusetts
pp. 94

IEEE Copyright Form (PDF)

pp. 95
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